1. Field of the Invention
The present invention generally relates to memory technology and, more particularly, to the use of wide data paths in memory densities over 4 megabits.
2. Description of the Prior Art
As memory technology continues to advance in capacities in an exponential fashion, the display resolution requirement is increasing in a linear fashion. While graphics developers have traditionally depended on wide data paths and interleaving to get sufficient graphics memory bandwidth, they are now left in a quandary as to how to take advantage of memory densities over about 4 megabits.
Raster-scan conversion techniques have traditionally been dependent on a wide data path connection to high speed Dynamic Random Access Memory (DRAM) or Video Random Access Memory (VRAM). Chip technology has evolved to the point that it is now a problem to take advantage of newer high density memory because the number of chips required to meet the capacity requirements is less than the number of chips required to provide a wide (fast) path to memory. Also the number of input/outputs and pins per chip, required to maintain the wide bandwidths in fewer chips, has practical limits. For low end two-dimensional Reduced Instruction Set Computer (RISC) based systems, this becomes an real problem at about the density level of 2 to 4 megabit memory chips. Thus, needed wide path between the Rasterizer/Display Controller and the frame buffer VRAM modules are no longer available to take advantage of new technology memory modules providing higher density and less chips.